library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


use work.cpu_utils.all;

entity CC is
	generic (
		Tpd: Time := unit_delay
	);
	port (
		--clock : in std_logic;
		N, Z: in bit;
		IR: in bit_vector (5 downto 0);
		st_cond: in bit;
		cond: out bit
	);
end entity CC;

architecture behavioral of CC is
begin
--process (clock) is begin
	--if clock'event and clock = '1' then
process (st_cond, N, Z, IR) is begin
		if	st_cond = '1' then
			if 
			(
				(IR = op_beq and Z='1')
				or	(IR = op_bnq and Z='0')
				or	(IR = op_blt and N='1')
				or	(IR = op_bgt and N='0')
				or	(IR = op_ble and ((Z='1')or(N='1')))
				or	(IR = op_bge and ((Z='1')or(N='0')))
				or (IR = op_jmp)	
				or (IR = op_jsr)	
			)
				then cond <= '1' after Tpd;
			else cond <= '0' after Tpd;
			end if;
		else null;
		end if;
	--end if;
end process;
end architecture behavioral;
